// edited from
// https://www.youtube.com/watch?v=WoMpQgQ8dqQ
module lab3bcdVerilog(clk, reset, count);
input clk, reset;
output reg [3:0] count;
always@(posedge clk or posedge reset)
if(reset)
count <= 4'b0; // 0
else if (count == 4'b1001) // 9
count <= 4'b0; // 0
else
count <= count + 1;
endmodule
module bcd_counter_dut();
wire clk;
reg reset;
wire [3:0] count;
initial begin reset =1; #50;
reset = 0;
end
lab3bcdVerilog bcd_cnt (clk, reset, count);
endmodule